10/21/2023 0 Comments Hyperdimensional space billiards![]() Hyperdimensional computing (HDC) is an emerging neuro-inspired computational framework. Furthermore, we study the effects of device, circuit, and architectural-level non-idealities on application-level accuracy with HDC. We also present a scalable and efficient architecture based on CAMs which supports the associative search of large HVs. Furthermore, for the first time, we experimentally demonstrate multi-bit, array-level content-addressable memory (CAM) operations with FeFETs. We present a multi-bit IMC system for HDC using ferroelectric field-effect transistors (FeFETs) that simultaneously achieves software-equivalent-accuracies, reduces the dimensionality of the HDC system, and improves energy consumption by 826x and latency by 30x when compared to a GPU baseline. Moreover, memory arrays used in IMC are restricted in size and cannot immediately support the direct associative search of large binary HVs (a ubiquitous operation, often over 10,000+ dimensions) required to achieve acceptable accuracies. ![]() Most existing IMC implementations of HDC are limited to binary precision which inhibits the ability to match software-equivalent accuracies. In-memory computing (IMC) can greatly improve the efficiency of HDC by reducing data movement in the system. In HDC, computational operations consist of simple manipulations of hypervectors and can be incredibly memory-intensive. ![]() Hyperdimensional computing (HDC) is a brain-inspired computational framework that relies on long hypervectors (HVs) for learning.
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